Refer to "FDS Copy Tool" at nesdev.parodius.com for a publicly-known technique. While it's not the best tech doc, you will have to see it anyway for info on modding the power module board inside the FDS disk drive.
Inside the FDS drive unit itself, you have the evil 3206 chip; this thing provides (among other things) the signals for the write head. Apparently, this chip needs to be bypassed completely, in order to write any in-coming data onto the disk. You might as well break the path between where this chip
Luckilly, the incoming signal is a stream of pulses that mark where a pulse should be recorded on the disk. This can be accomplished by feeding the write data into a simple positive-edge triggered toggle flip-flop, and powering the 2 write head lines with the complimentary logic outputs on the flip-flop (polarity of signals is irrelivant).
The outputs of the flip-flop must be forced to be equal, during the times when writing is undesired. With TTL comp. out. flip-flops, this _can_ be accomplished by using taboo and activating set and reset flip-flop inputs simultaniously, though this may cause the chip to race for a few dozen nanoseconds after deactivation of the RS inputs.
The clean solution is to use either:
A) two- 2-input (N)and/or gates. The gates will be tied in series with the flip-flop's comp. output path to the write head wires. the other unused inputs on the gates will be your disable write heads.
B) 1- 1 of n decoder with disable inputs. use two decoded addresses from feeding the flip-flop's output line onto a decoder input address pin.
The complimentary write signal drive outputs must be either open-collector, or have a high drive output for both sink and source (in this case, you'll remove the 2- 200 ohm resistors pulling up the write head lines to +5VDC).
The /ready, /write, and /write enable (from switch) signals must all be zero, in order for the write head outputs to function.
My mod only used 2 simple standard TTL chips: 7445, and 7476 (which is much less parts than the aformentioned public mod shows it being done with). The 7445 is a 4-line to 10-line address decoder with high-current open-collector outputs. The 7476 is a dual pos-edge trig. JK flip-flop.
I fed the write data signal right into the input of one of the flip-flops (with J, K, /R, and /S inputs all tied to logical 1), and fed the Q output into address decode input line 0 on the 7445. I fed the /ready, /write, and /write enable signals to the remaining 3 address decode input lines, and hooked up the decoded outputs from lines 0 and 1 up to the write head lines.
Feel free to ask more questions if this explanation is not clear enough.